首頁外文書人文科普 〉CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test
商品訊息
作者書籍
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test


作者  /  Andrei Pavlov/ Manoj Sachdev

出版社 / SPRINGER VERLAG

出版日期 / 2008/06/23

商品語言 / 英文

裝訂 / 精裝

定價 / NT$9,405

售價 / NT$ 9,405 ※ 特價商品,不再折扣

※ 無庫存


CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test 其它優惠/消息


introduction all_character


內容簡介

The monograph will be dedicated to SRAM (memory) design and test issues in nano-scaled technologies by adapting the cell design and chip design considerations to the growing process variations with associated test issues. Purpose: provide process-aware solutions for SRAM design and test challenges.







詳細資料

誠品26碼 /2681257464005
ISBN 13 /9781402083624
ISBN 10 /1402083629
EAN /9781402083624

頁數194
尺寸15.6X1.3X23.4CM
裝訂精裝
級別
語言英文
成份




Share/Save/Bookmark

查看全台書店有無此商品