RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design | 誠品線上

RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design

內容簡介

內容簡介 This book is both a tutorial and a reference for engineers who use the SystemVerilog Hardware Description Language (HDL) to design ASICs and FPGAs. The book shows how to write SystemVerilog models at the Register Transfer Level (RTL) that simulate and synthesize correctly, with a focus on proper coding styles and best practices.SystemVerilog is the latest generation of the original Verilog language, and adds many important capabilities to efficiently and more accurately model increasingly complex designs. This book reflects the SystemVerilog-2012 2017 standards. This book is for engineers who already know, or who are learning, digital design engineering. The book does not present digital design theory; it shows how to apply that theory to write RTL models that simulate and synthesize correctly. The creator of the original Verilog Language, Phil Moorby says about this book (an excerpt from the book's Foreword): "Many published textbooks on the design side of SystemVerilog assume that the reader is familiar with Verilog, and simply explain the new extensions. It is time to leave behind the stepping-stones and to teach a single consistent and concise language in a single book, and maybe not even refer to the old ways at all! If you are a designer of digital systems, or a verification engineer searching for bugs in these designs, then SystemVerilog will provide you with significant benefits, and this book is a great place to learn the design aspects of SystemVerilog."

作者介紹

作者介紹 Stuart Sutherland provides expert SystemVerilog training workshops and consulting services. Stuart has more than 30 years of experience with Verilog and SystemVerilog. He has served as the technical editor for every version of the IEEE Verilog and SystemVerilog Language Reference Manuals (LRMs). Stuart founded Sutherland HDL, Inc. in 1992, located in Tualatin, Oregon, USA. Stuart has authored and co-authored numerous papers on these languages (available at www.sutherland-hdl.com). He has authored the books: "The Verilog PLI Handbook","Verilog-2001: A Guide to the New Features of the Verilog HDL, and "SystemVerilog for Design: A Guide to Using the SystemVerilog Enhancements to Verilog for Hardware Design" (co-authored with Simon Davidmann and Peter Flake), and "Verilog and SystemVerilog Gotchas:101 Common Coding Error and How to Avoid Them" (co-authored with Don Mills)". Stuart holds a Bachelor's Degree in Computer Science with an emphasis in Electronic Engineering Technology from Weber State University (Ogden, Utah) and Franklin Pierce College (Nashua, New Hampshire), and a Master's Degree in Education with an emphasis on eLearning course development from Northcentral University (Prescott, Arizona).

商品規格

活動

• 7/20前 全站滿$1,500折$150
• 7/20前 全站滿$3,500折$420
• 7/20前 全站滿$2,200折$220