Verilog by Example: A Concise Introduction for FPGA Design | 誠品線上

Verilog by Example: A Concise Introduction for FPGA Design

作者 Blaine Readler
出版社 Ingram International Inc
商品描述 Verilog by Example: A Concise Introduction for FPGA Design:Apracticalprimerforthestudentandpracticingengineeralreadyfamiliarwiththebasicsofdigitaldesign,theref

內容簡介

內容簡介 A practical primer for the student and practicing engineer already familiar with the basics of digital design, the reference develops a working grasp of the verilog hardware description language step-by-step using easy-to-understand examples. Starting with a simple but workable design sample, increasingly more complex fundamentals of the language are introduced until all major features of verilog are brought to light. Included in the coverage are state machines, modular design, FPGA-based memories, clock management, specialized I O, and an introduction to techniques of simulation. The goal is to prepare the reader to design real-world FPGA solutions. All the sample code used in the book is available online. What Strunk and White did for the English language with "The Elements of Style," VERILOG BY EXAMPLE does for FPGA design.

商品規格

書名 / Verilog by Example: A Concise Introduction for FPGA Design
作者 / Blaine Readler
簡介 / Verilog by Example: A Concise Introduction for FPGA Design:Apracticalprimerforthestudentandpracticingengineeralreadyfamiliarwiththebasicsofdigitaldesign,theref
出版社 / Ingram International Inc
ISBN13 / 9780983497301
ISBN10 /
EAN / 9780983497301
誠品26碼 /
裝訂 / P:平裝
重量(g) / 181.4
頁數 / 124
語言 / 3:英文
級別 / N:無
尺寸 / 22.6X15.0X1.0CM

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